Modern consumer electronics, such as smart phones, personal digital assistants, and location based services devices, as well as enterprise electronics, such as servers and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Every new generation of integrated circuits with increased operating frequency, performance and the higher level of large scale integration have underscored the need for back-end semiconductor manufacturing to provide more solutions involving the integrated circuit itself.
Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on package technologies while others focus on improving the semiconductor technologies and manufacturing. Both approaches may include additional processing of the integrated circuits to better match the targeted package.
Integrated circuit density continues to be limited by the “real estate” available for mounting individual integrated circuits on a substrate. Even larger form factor systems, such as personal computers, compute servers, and storage servers, need more integrated circuits in the same or smaller “real estate”. Particularly acute, the needs for portable personal electronics, such as cell phones, digital cameras, music players, personal digital assistants, and location-based devices, have further driven the need for integrated circuit density. Manufacturing integrated circuits having a thinner profile is one approach taken to increase integrated circuit density in the ever shrinking “real estate”. The integrated circuits may undergo thinning process at the wafer level.
Wafer level thinning performs thinning on the inactive or backside of the wafer through processes such as lapping, grinding, or back-lapping. However, the demands for large volume of integrated circuits push wafer fabrication to increase diameters that exacerbating wafer warpage or bowing. The wafer warpage leads to uneven thinning and breakage not only during wafer level thinning but also throughout manufacturing handling.
As the demand for smaller electronic devices grows, manufacturers are seeking ways to reduce the size and weight of the packaged integrated circuits. To meet these needs, packaging technologies are shifting towards thinner profiles with more die stacking and/or wafer level packaging in bare die form. This drives the demand for better wafer thinning technology to achieve a very thin wafer thickness.
Existing technology has attempted to reduce wafer stress during wafer thinning processes so that higher wafer production can be achieved. In addition to reducing wafer stress, some attempts also address wafer strength during processing hoping to avoid the effects of wafer stress. Dicing Before Backgrind (DBG) is an attempt to obtain an ultra thin wafer thickness.
However, DBG approach reduces wafer stress within the wafer itself but presents other problems. DBG typically requires additional steps and materials. For example, DBG requires an additional backside die attach film (DAF) cut step after the back-grinding step. Also, DBG typically requires a dedicated laser for cutting the die attach film. Moreover, DBG requires special alignment systems to mitigate the difficulties cutting the die attach film of the separate dice. Another factor is the increase in cost from grinding tape required to be thick and have high adhesion strength to hold the separated dice.
Thus, a need still remains for a wafer system providing low cost manufacturing, improved yield, and thinner height for the integrated circuits. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.